The performance of an OFET structure is generally improved when the capacitance between the gate and the channel increases. This can be achieved by making the dielectric layer between the gate and channel as thin as possible. However, as the dielectric layer is made thinner, there is an increased probability of shorting between the first conductor source/drain layer and the second conductor gate layer caused by an increased likelihood of pinholes in the thinner dielectric.
Such pinholes are particularly prevalent in polymer dielectric layers and will inadvertently permit shorting of a first layer conductor to a second layer conductor in the OFET. In the prior art, the dielectric layer can be increased in thickness or deposited a second time in order to reduce incidences of these pinholes. However, both of these approaches undesirably result in a thicker gate dielectric layer, significantly decreasing the performance of the transistor. In the prior art, dielectric layer might alternatively be replaced with a high-K dielectric layer. When the dielectric constant of the dielectric layer is increased, a comparable gate capacitance is achieved with a thicker dielectric layer. However, dielectric compatibility with the organic semiconductor is crucial in OFET devices. High-performing organic semiconductors tend to be compatible only with low-K dielectrics.
What is desired, therefore, is an OFET-compatible fabrication method and corresponding OFET structure for reducing the probability of pinholes without significantly changing the capacitance between gate and channel.